This invention relates in general to synthesizers, commonly referred to as "frequency synthesizers", which produce a periodic signal the frequency of which is selectable over a specified range, and in particular to digital frequency synthesizers which employ, in their signal generation process, a selectable-increment counting means to progressively step through a memory containing signal synthesis information.
In conventional digital frequency synthesizers only a single processing path is used to synthesize the signals. A single selectable-increment counting means is used to generate a series of arithmetically progressive memory addresses which are used to index the contents of a single memory, such as a read-only memory (ROM), which contains digitized samples of the signal being synthesized. The digitized samples read from the memory are converted to a sequence of corresponding analog levels, and the analog levels are filtered to remove undesirable high frequency components. The result is a synthesized continuous periodic signal, the frequency of which is determined primarily by the samples from the memory.
In such conventional digital frequency synthesizers, an accumulator is often used as the selectable-increment counting means for progressively indexing the memory. For purposes of this specification, an accumulator is a combination of an arithmetic operator and a data storage register in which the results of arithmetic operations are stored in response to a loading signal, a signal which loads th output of the arithmetic operator into the storage register. The data stored in the register is fed back to the arithmetic operator as an operand (e.g. addend or minuend) for a next succeeding arithmetic operation. Often an accumlator comprises a plurality of integrated circuits connected as serial or parallel operators.
In the operation of an accumulator used as a selectable-increment counting means for frequency synthesis, an increment value derived from, and unique to, a frequency selected by an operator is saved, and the saved increment value is continuously communicated to the accumulator's arithmetic operator as an addend or subtrahend. In this way the saved increment value is continuously added to or subtracted from the contents of the storage register. As a plurality of loading signals (which in this case are more appropriately called "clock signals") are sent to the storage register, the output of the arithmetic operator progresses arithmetically in steps equal to the saved increment value. The contents of the storage register likewise progresses arithmetically (up or down) but always one step behind the arithmetic operator. The accumulator output, which is generally designated to be the contents/output of the storage register, is communicated to the memory as a series of addresses, and as the output of the accumulator increases or decreases by uniform steps equal to the derived increment, the memory is progressively indexed.
The frequency at which the accumulator's storage register is loaded, i.e. the frequency of the clock signal, is actually the counting rate of such an accummulator functioning as a selectable-increment counter. The bandwidth (maximum effective counting rate) of such an accumulator is primarily determined by the bandwidth of the arithmetic operator, the bandwidths of data storage registers typically being orders of magnitude greater than arithmetic operators.
Heretofore, the speed, performance and bandwidth of such conventional digital frequency synthesizers have been primarily limited by the bandwidth, or conversely the throughput delay, of the counting accumulator which is the slowest element with its many gate levels through which information must propagate and settle-out in order to form a valid memory address. In effect the accumulator is the bottle neck because of its propagation delay.
This invention presents a digital frequency synthesizer which is not so bandwidth limited. It has a unique set-up process and multiple processing paths by which the processing of multiple samples is overlapped to overcome the inherent delays of the above-described counting accumulators, resulting in a synthesizer with an overall bandwidth many times greater than conventional synthesizers.
Other advantages and attributes of this invention will be readily discernible upon the reading of the text hereinafter.